Comparison of Scalable Montgomery Modular Multiplication Implementations Embedded in Reconfigurable Hardware

International audienceThis paper presents a comparison of possible approaches for an efficient implementation of Multiple-word radix-2 Montgomery Modular Multiplication (MM) on modern Field Programmable Gate Arrays (FPGAs). The hardware implementation of MM coprocessor is fully scalable what means that it can be reused in order to generate long-precision results independently on the word length of the originally proposed coprocessor. The first of analyzed implementations uses a data path based on traditionally used redundant carry-save adders, the second one exploits, in scalable designs not yet applied, standard carry-propagate adders with fast carry chain logic. As a control unit and a platform for purely software implementation an embedded soft-core processor Altera NIOS is employed. All implementations use large embedded memory blocks available in recent FPGAs. Speed and logic requirements comparisons are performed on the optimized software and combined hardware-software designs in Altera FPGAs. The issues of targeting a design specifically for a FPGA are considered taking into account the underlying architecture imposed by the target FPGA technology. It is shown that the coprocessors based on carry-save adders and carry-propagate adders provide comparable results in constrained FPGA implementations but in case of carry-propagate logic, the solution requires less embedded memory and provides some additional implementation advantages presented in the paper

Venous hemodynamics in neurological disorders: an analytical review with hydrodynamic analysis.

Venous abnormalities contribute to the pathophysiology of several neurological conditions. This paper reviews the literature regarding venous abnormalities in multiple sclerosis (MS), leukoaraiosis, and normal-pressure hydrocephalus (NPH). The review is supplemented with hydrodynamic analysis to assess the effects on cerebrospinal fluid (CSF) dynamics and cerebral blood flow (CBF) of venous hypertension in general, and chronic cerebrospinal venous insufficiency (CCSVI) in particular.CCSVI-like venous anomalies seem unlikely to account for reduced CBF in patients with MS, thus other mechanisms must be at work, which increase the hydraulic resistance of the cerebral vascular bed in MS. Similarly, hydrodynamic changes appear to be responsible for reduced CBF in leukoaraiosis. The hydrodynamic properties of the periventricular veins make these vessels particularly vulnerable to ischemia and plaque formation.Venous hypertension in the dural sinuses can alter intracranial compliance. Consequently, venous hypertension may change the CSF dynamics, affecting the intracranial windkessel mechanism. MS and NPH appear to share some similar characteristics, with both conditions exhibiting increased CSF pulsatility in the aqueduct of Sylvius.CCSVI appears to be a real phenomenon associated with MS, which causes venous hypertension in the dural sinuses. However, the role of CCSVI in the pathophysiology of MS remains unclear

Testing of PLL-based True Random Number Generator in ChangingWorking Conditions

International audienceSecurity of cryptographic systems depends significantly on security of secret keys. Unpredictability of the keys is achieved by their generation by True Random Number Generators (TRNGs). In the paper we analyze behavior of the Phase-Locked Loop (PLL) based TRNG in changing working environment. The frequency of signals synthesized by PLL may be naturally influenced by chip temperature. We show what impact the temperature has on the quality of generated random sequence of the PLL-based TRNG. Thank to analysis of internal signals of the generator we are able to prove dependencies between the PLL parameters, statistical parameters of the generated sequence and temperature. Considering the measured results of experiments we form a new requirement in order to improve the robustness of the designed TRNG

Hardware-Software Codesign in Embedded Asymmetric Cryptography Application

This paper presents a case study of a hardware-software codesign of the RSA cipher embedded in reconfigurable hardware. The 16 and 32-bit soft cores of Altera's Nios RISC processor are used as the basic building block of the proposed complete embedded solutions

MONTGOMERY MULTIPLICATION COPROCESSOR ON RECONFIGURABLE LOGIC

In this paper we introduce a scalable Montgomery Multiplication (MM) coprocessor implemented in reconfigurable hardware. A way of connection to Altera Nios embedded processor and some improvements of design are presented. 1

Embedded True Random Number Generator in Actel FPGA

In high level security systems the unpredictability and unrepeatability of a random sequence is ensured by its generation in a true random number generator (TRNG) based on a physical phenomenon. Although the method based on randomness extraction from tracking jitter of phase-locked loop (PLL) is universal and applicable in wide scale of FPGAs or other digital circuits with analog PLLs, only implementations in Altera FPGAs were presented so far. This paper summarizes possible TRNG configurations and relation between PLL and TRNG parameters. Next, we analyze the possibility to implement presented class of TRNGs in Actel FPGAs and we provide the step-by-step instructions for the design of the TRNG in the selected family. The Actel FPGAs are shown to be a suitable target platform for the discussed type of TRNG

Area-time efficient hardware architecture for factoring integers with the elliptic curve method

Since the introduction of public key cryptography, the problem of factoring large composites is of increased interest. The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factoring large integers is the General Number Field Sieve (GNFS). One important step within the GNFS is the factorization of mid-size numbers for smoothness testing, an efficient algorithm for which is the Elliptic Curve Method (ECM). Since the smoothness testing is also suitable for parallelization, it is promising to improve ECM via special-purpose hardware. We show that massive parallel and cost efficient ECM hardware engines can improve the cost-time product of the RSA moduli factorization via the GNFS considerably. 1 The computation of ECM is a classical example for an algorithm that can be significantly accelerated through special-purpose hardware. In this work, we thoroughly analyze the prerequisites for an area-time efficient hardware architecture for ECM. We present an implementation of ECM to factor numbers up to 200 bits, which is also scalable to other bit lengths. ECM is realized as a software-hardware co-design on an FPGA and an embedded microcontrolle